                           Broadcom Bootcode Firmware 
                                    For 
                  
                 BCM57762, BCM57766, BCM57782 and BCM57786x
                                  

                   Copyright (c) 2011-2012 Broadcom Corporation
                          All rights reserved.

                          
---------------------------------------
Version 1.12 April 23, 2012 
---------------------------------------

   1. Problem: 
      Reg 0x3690[19:16] is corrupted during A1 reboot test.
	  
      Change:
      Bootcode will hard code data to Reg 0x3690 after booting up.
    
     Enhancements:
     =============
     1. Disabled SW LTR support per LSI team request.
                         
--------------------------------------
Version 1.11 March 26, 2012 
---------------------------------------

   Enhancements:
   =============
   1. Add 57762, 57766, 57782 and 57786x A1 support.
   
---------------------------------------
Version 1.09 March 1, 2012 
---------------------------------------

   Fixes:
   ======
   1. Problem: CQ 60995 
       Cont00061694 - ASF is not working when memory has been removed from system.
	  
      Cause:
      When system boot up without memory, the CPMU slow the Mac clock to  6.25 MHz.
      It is too slow for ASF firmware to run.
      
      Change:
       Select Mac Clock Switch Speed in Link Aware Power Mode Clock Policy 
       Register (offset: 0x3610), D0u Clock Policy Register (offset: 0x3614) and Link Idle Power 
       Mode Clock Policy Register (offset: 0x3618) to be 62.5MHz when PXE or Management 
       Firmware is enabled.  This will prevent the Mac Clock being slowed down by the CPMU.
       This will also prevent a slow firmware loading from NVRAM.

                            
---------------------------------------
Version 1.08 February 29, 2012 
---------------------------------------

   Enhancements:
   =============
   1. Modified the polling loop in set_mrrs() function to time out at 3 sec to prevent deal lock.
       The set_mrrs() function will read back and retry for a maximum of 3 sec to make sure 
       the MRRS data is successfully being written to the register.

---------------------------------------
Version 1.07 February 16, 2012 
---------------------------------------

   Fixes:
   ======
  1. Problem: CQ 60995 
      The performance numbers in Tx are not good enough when the ASF and PXE enabled in NVRAM. 
	  
      Cause:
      BC forces the Mac Clock speed to the highest when ASF or PXE is enabled.  The BC updates
      the CPMU control register at 0x3600 and then forces the Mac Clock by setting the 
      MAC Clock Speed Override Enable bit in Clock Override Enable Register at offset 
      0x3628 back to back.  Such action seems to be upsetting the TX performance. 
      
      Change:
      Based on the test results, BC will enable Link Speed Mode and set the Link Speed Clock Policy
      registers to 62.5MHz to work around this issue.      
      
----------------------------------------
Version 1.05 February 09, 2012 
---------------------------------------

   Enhancements:
   =============
   1. BC poll for TX idle and set/clear the 0x36B0[7].	
   
   2. Set Reg36BC[3] to disable this idle condition
      from the EEE idle detection logic
   
----------------------------------------
Version 1.04 January 31, 2012 
---------------------------------------

   Fixes:
   ======
   1. Problem: CQ 60930
      Aspen+ NIC: EEE not functioning properly after system Suspend/Resume(S3/S4).
	  
	  Cause:
      BC has zeroed out EEE mode control register 0x36b0 when system is resuming 
      from S3/S4 (with EEE disabled in nvram), this makes device is unable to 
      determine link partner's EEE capability anymore.	  

      Change:
      BC will clear EEE_MODE_USER_LPI_ENABLE (BIT_7) of 0x36b0 instead of zeroing
      out the register when system resuming from S3/S4. 	  
  
   2. Problem: CQ 60995 
      The performance numbers in Tx are not good enough when the ASF and PXE enabled in NVRAM. 
	  
      Cause:
      BC forces the Mac Clock speed to the highest when ASF or PXE is enabled.  The BC updates
      the CPMU control register at 0x3600 and then forces the Mac Clock by setting the 
      MAC Clock Speed Override Enable bit in Clock Override Enable Register at offset 
      0x3628 back to back.  Such action seems to be upsetting the TX performance. 
      
      Change:
      Based on the test results, BC does not need to force the Mac Clock in order to run PXE.
      Therefore, BC will not force the Mac Clock when PXE is enabled.	  
	  
--------------------------------------------
Version 1.03 - January 09, 2012   
--------------------------------------------

   Enhancements:
   =============
   
   1. Disable the SWR Burst Mode.
   
--------------------------------------------
Version 1.02 - January 03, 2012   
--------------------------------------------

   Fixes:
   ======
   1. Problem: CQ 60506
      The performance numbers in Tx are not good enough when the ASF enabled in NVRAM. 
	  
      Cause:
      BC forces the Mac Clock speed to the highest when ASF is enabled.  The BC updates
      the CPMU control register at 0x3600 and then forces the Mac Clock by setting the 
      MAC Clock Speed Override Enable bit in Clock Override Enable Register at offset 
      0x3628 back to back.  Such action seems to be upsetting the TX performance. 
      
      Change:
      After updating the CPMU control register, BC will not force the Mac Clock speed right
      away.  BC will force the Mac Clock speed right before loading the ASF firmware from
      NVRAM.	  
   						  
--------------------------------------------
Version 1.01 - December 09, 2011   
--------------------------------------------

   Enhancements:
   =============
   
   1. Hide MS function in 57766.
   
   Note:
   =====
   This release is for 57766 only.
   
--------------------------------------------
Version 1.00 - December 08, 2011   
--------------------------------------------

   Enhancements:
   =============

   1. Adding 57786x and 57782 supports.
   
--------------------------------------------
Version 0.02 - October 19, 2011   
--------------------------------------------

   Enhancements:
   =============

   1. Do not modify CR MRRS at Reg 0x6c.
    
--------------------------------------------
Version 0.01 - September 30, 2011   
--------------------------------------------
   Initial engineering release

  This is a branch of 57765 v1.48
   
   
   Enhancements:
   =============
   1. Remove CQ45376 workaround.
   
   2. Change the Function 0 MRRS to 4KB
   
   3. Set MSI-X Table size according to Reg 6888[27].
      For EAV SKU, program the MSI-x Table Size with 6
      For non-EAV Sku, program the MSI-x Table Size with 5

   4. Enable LTR support.
   
   5. Enable VPD support.
   
   6. Remove "Not to power down the refclk pad during clkreq" workaround.
   
   7. Program the device ID (0x16A3) for the Function 0 when 3690[30] is set to 1.
.
